Size reduction of metal-oxide-semiconductor field-effect transistors (MOSFETs) has enabled the continued improvement in speed performance, density, and cost per unit function of integrated circuits. Semiconductor industry is also in the era of transitioning from 2D transistors, which are often planar, to 3D transistors using a three-dimensional gate structure. In 3D gate structures, the channel, source and drain are raised out of the silicon substrate and the gate is wrapped around the channel on three sides. One such type of 3D transistors is known as FinFET (Fin field-effect transistor), in which the channel connecting the source and drain is a thin “fin” jutting out of the substrate. The gate controls a flow of charge carriers in the channel more strongly because it extends over three sides of the fin shaped channel, rather than only across the top of a more traditional planar channel. This results in the current being constrained to the raised channel, thereby preventing electrons from leaking.
Group III-V compound semiconductor materials have been used for forming the fin channel structure due to their higher electron mobility and saturation velocity than silicon. However, the epitaxial growth of III-V compound semiconductor materials upon silicon substrate presents challenges and problems. For example, crystal defects are generated due to lattice mismatch and thermal mismatch between the III-V epitaxial layer (i.e., the fin channel structure) and the silicon substrate. When the lattice mismatch exceeds a few percent, the strain induced by the mismatch develops at the III-V epitaxial layer and substrate interface as well as in the III-V epitaxial layer and generates defects, which could be in the form of dislocations or stacking faults.
Various buffer layers and barrier layers have been utilized between the III-V epitaxial layer and the silicon substrate in attempts to accommodate or relieve the strain induced by the lattice mismatch between the III-V epitaxial layer and the silicon substrate. In practice, however, these buffer layers and barrier layers are unable to completely prevent dislocations and stacking faults from propagating into the III-V epitaxial layer. In addition, it has also been observed that a leakage path from the source to the drain of the transistor may develop in the barrier and/or buffer layers, which causes increased off-state leakage current and degrades the ability of the transistor to completely turn off. As a result, the performance of the transistors is degraded.
Therefore, there is a need in the art to provide an improved fabrication technique for transistors to prevent undesired leakage and defects generated between the III-V epitaxial layer and the silicon substrate.